Electronic Design Automation

This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results.

This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use.

This paper details how the Calibre xACT 3D extraction solution addresses the extraction challenges for design signoff at advanced nodes.

What Is CFA and Why Do I Need It? This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.

This paper will examine the implementation and demonstrate the benefits of eqDRC through a variety of examples comparing traditional DRC with eqDRC approaches.

The Mechanical Analysis Division of Mentor Graphics (formerly Flomerics) provides the world's most advanced computational fluid dynamics products. Our simulation software and consultancy services eliminate mistakes, reduce costs, and accelerate and optimize designs involving heat transfer and fluid flow before physical prototypes are built.

While the new generation of self-service applications for the Web and IVR is excellent, successful self-service programs will depend on giving customers choices and striking the right balance.

"As the number of enhancements to various Hardware Description Languages (HDLs) has increased over the past year, so too has the complexity of determining which language is best for a particular design. Many designers and organizations are contemplating whether they should switch from one HDL to another. This paper compares the technical characteristics of three, general-purpose HDLs.

Join us at ESC Boston, September 21-24 at the Hynes Convention Center, in Boston, MA. Expo registration is FREE, and advanced registration pricing is still available for conference packages.

Interest in DO-254 first occurred in Europe and has since spread to the US commercial aircraft industry. If you are being asked about your company's DO-254 direction and compliance, but have been overwhelmed with information on the subject, then this article is for you.

The Business Ready Configurations for Dell PowerEdge blade servers, Dell EqualLogic SAN, and VMware Infrastructure provides a detailed reference architecture for deploying and using VMware virtualization on Dell blades and iSCSI storage environments. The Dell PowerEdge M1000e supports the recently announced 11th generation Dell PowerEdge M610 and M710 blade servers based on the new Intel Xeon processors.

Reaching tight alignment with these objectives is not an easy task. Yet, we believe when a communication services provider integrates these customer-centric objectives into the design of its converged solution, its business customers will no longer ask if the solution will meet their objectives. Rather, the question becomes one of execution: how and when to move to a converged communication solution. converged solution. From these attributes, a framework to measure and compare providers' converged solutions emerges. We will conclude with a review of Sprint's approach to offering true convergence to business and government customers.

A powerful signal integrity analysis tool must be flexibility, easy to use and integrated into an existing EDA framework and design flow. In addition, it is important for the tool to be accurate enough. This report reviews a validation study for the Mentor Graphics HyperLynx 8.0 PI tool to establish confidence in using it for power integrity analysis.

For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.

High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.

The success of any consumer electronic device depends to a large extent on the appeal of the user interface (UI) and how easy the device is to use. Studies show that good cosmetic design can encourage users to explore the full range of features and often engenders the perception that a product is easier to use. So if the benefits of a great looking, easy-to-use UI are so clear, why are so many products still falling short of customer expectations? The solution lies in taking a fresh new approach a consumer electronic device UI plays. By identifying common UI functionality and implementing it in a reusable and customizable way, we can make it far easier for embedded engineers to deliver visually engaging and easy-to-use consumer electronic products.

Moving to C++ presents opportunities for higher programmer productivity. The requirements of embedded systems, however, demand that the adoption of C++ be carefully measured for the performance impact of run-time costs present in C++, but not in C. This talk suggests strategies for developers who are starting their acquaintance with C++.

To accommodate increasingly dense technology environments, increasingly critical business applications, and increasingly stringent service level demands, data centers are typically engineered to deliver the highest-affordable availability levels facility-wide. Within this monolithic design approach, the same levels of mechanical, electrical, and IT infrastructure are installed to support systems and applications regardless of their criticality or business risk if unplanned downtime occurs. Typically, high redundancy designs are deployed in order to provide for all eventualities. The result, in many instances, is to unnecessarily drive up both upfront construction or retro-fitting costs and ongoing operating expenses.

Comprehensive guidelines for cost-effective die casting production. Written for OEM product designers and engineers to aid in optimizing their part designs and specifications for custom production in Aluminum, Magnesium, and Zinc die casting alloys.

Ultra High Speed Internet, TV and local/long distance phone services combined into 1 superior service.

"ModelSim ASIC and FPGA design Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC.

PADS DxDesigner A sophisticated yet scalable design environment fully intergrated with PADS

Interaction between electrical and mechanical engineering is more important than ever to achieve “first time” success for your design.

Electronics and Software Engineering are quickly merging with traditional Mechanical Engineering to create a new paradigm in auto manufacturing: Mechatronics. Industry experts predict that this shift will bring about profound advances in automotive product development. Unfortunately, existing IT and process infrastructures do not provide sufficient capabilities to support the new paradigm: multiple data silos, a lack of standardized processes, and integration issues on a tool level (Mechanical, Electronic, Software) continue to pose serious obstacles to development efficiency, and remain a frequent source of delays, quality issues and cost increases.

Through a combination of integrated hardware and software components, ARM TrustZone* technology provides the basis for a highly-protected system architecture targeted specifically at securing consumer products such as mobile phones, PDAs, set-top boxes or other systems running open Operating Systems (OS), such as Symbian OS, Linux and Windows CE.